This disclosure relates to data processing and data storage, and more specifically, to determining a threshold voltage shift (TVS) of a read threshold voltage for a unit of data storage in a non-volatile memory system. Still more particularly, the disclosure relates to determining the TVS of the unit of data storage at a lower bit error rate (BER) by intelligently applying a mitigation strategy, which may include performing a dummy configuration read and performing a configuration read within a time window following the dummy configuration read.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure. The amount of charge on the floating gate modulates the threshold voltage of the transistor. By applying a proper read voltage and measuring the amount of current, the programmed threshold voltage of the memory cell can be determined, and thus the stored information can be detected. Memories storing one, two, three and four bits per cell are respectively referred to in the art as Single Level Cell (SLC), Multi-Level Cell (MLC), Three Level Cell (TLC), and Quad Level Cell (QLC) memories. In a typical implementation, a NAND flash memory array includes multiple physical die, which can each include multiple planes. These planes in turn each contain multiple blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each containing a multiplicity of memory cells. By virtue of the physical arrangement of the word and bit lines utilized to access memory cells, flash memory arrays have generally been programmed on a page basis, but erased on a block basis.
In multi-level (i.e., MLC, TLC and QLC) NAND flash memory, information is stored by programming the memory cells to various quantized threshold voltage levels according to the device's programming algorithm, which maps the binary bit values to discrete threshold voltage levels. In response to a page read command, the binary bit values are retrieved by applying appropriate read voltages that divide the programmed threshold voltage window into discrete regimes and by then applying a reverse mapping between the detected threshold voltage levels and the corresponding binary bit values. Over the lifetime of a multi-level NAND flash memory device, the distributions of programmed threshold voltage generally become degraded due to effects such as wear or retention on the memory cells. Consequently, it is generally desirable to adapt or shift the read voltage thresholds defining the various bit values over time to compensate for these effects and to extend the useful life of the NAND memory device.